The present invention relates generally to estimating the spatial characteristics of integrated circuits. Spatial characteristics can include a length, width, height, critical dimension, side wall angle and/or profile, line edge, line width, roughness, shape contour, undercut, foot, a complete profile in one or more dimensions, or other measurement of a feature. More specifically, the present disclosure provides methods, program products, and systems for estimating a spatial characteristic of an integrated circuit, which can use one or more artificial neural networks.
An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components can be interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Fabrication foundries (“fabs”) can manufacture ICs using photolithographic processes. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating of a substrate. To fabricate an IC, photomasks are created using an IC design layout as a template. The photomasks contain the various geometries (i.e., features) of the IC design layout, and these geometries can be separated with layers of photoresist material. The various geometries contained on the photomasks correspond to the various base physical IC elements that make up functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements that are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
A pitch specifies a sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature. The pitch for a particular IC structure is generally predetermined and fixed by design. Depending on the photolithographic process being used, factors such as optics and wavelengths of light or radiation restrict how small the distance between two features (also known as “critical dimension”) can be before features can no longer be reliably printed to a wafer or mask. Thus, the pitch limits the largest size of any features that can be created on a wafer.
Several constraining factors in traditional photolithographic processes limit their effectiveness as circuit complexity continues to increase and transistor designs become more advanced and ever smaller in size (i.e., density shrink). Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the light/optical tools or techniques available for use may be limited due to physical constraints (e.g., wavelength and aperture) of the photolithographic process. Further, physical probes (e.g., atomic force microscopy (AFM) probes) for measuring the spatial characteristics may have limited effectiveness for IC elements smaller than some dimensions of the probe. Other measuring techniques, such as the use of a scanning electron microscope (SEM), may emit electrons which reduce one or more dimensions of the IC being measured (e.g., by degrading the material composition of a particular layer). Despite the limitations of these techniques, measuring the spatial characteristics of an IC with high accuracy can ensure the quality and reliability of each feature in an IC product produced from a manufacturing line.